Efficient fault ride-through scheme for three phase voltage source inverter-interfaced distributed generation using DC link adjustable resistive type fault current limiter


A novel fault ride through (FRT) method for three phase voltage source inverters.

One single set of AR-FCL in DC side of the VSI to improve its FRT capability.

Detailed analytical analysis in one switching carrier period.

Extensive simulation results in PSCAD/EMTDC software under LLLG, LLG and LG faults.

Demonstrating effectiveness of the proposed FRT scheme by an experimental setup.


This paper proposes a DC link adjustable resistive type fault current limiter (AR-FCL) based-voltage source inverter (VSI) fault ride-through (FRT) capability improvement, which is new approach of using FCLs. Instead of using three phase FCLs in AC side of the VSI, just one single phase proposed AR-FCL is connected in series with DC side of the VSI. During normal operation, the AR-FCL does not have effect on the VSI performance. When fault happens, the AR-FCL limits AC side fault currents in faulty phases to safe area operation of semiconductor devices of inverter, and does not affect healthy lines. The desired limited fault current value can be achieved by discharging and charging of DC inductor using large resistance, which enters and retreats by turning off and on of the AR-FCL’s semiconductor switch, respectively. The VSI does not require to change its control strategy from normal to fault mode operation. Consequently, wind-up and latch-up problems are smoothed. Analytical analysis is provided in each switching interval to highlight effectiveness of the AR-FCL on the VSI fault current limitation. The proposed FRT scheme is validated through both extensive simulation studies in PSCAD/EMTDC environment and three-phase experimental prototype for all symmetrical, asymmetrical, and transient faults.


  • Voltage-sourced inverter (VSI);
  • Symmetrical and asymmetrical grid faults;
  • Fault ride-through (FRT);
  • Adjustable resistive type fault current limiter (AR-FCL)

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